Array substrate, liquid crystal panel and liquid crystal display

ABSTRACT

An array substrate comprises a first substrate and a plurality of gate lines and a plurality of the data lines provided on the first substrate, the plurality of gate lines and the plurality of the data lines define a plurality of pixel units arranged into a matrix form. Each of the plurality of pixel units comprising: a first electrode having slits, comprising two or more regions where the slits have the different tilt degrees; a second electrode; and a thin film transistor switch, wherein the first electrode and the second electrode are used to form a horizontal electric field for driving liquid crystal molecules, the gate line and the thin film transistor switch are arranged between each two regions of the first electrode, and the thin film transistor switch is controlled by the gate line to operate each region of the first electrode.

BACKGROUND

Embodiments of the present invention relate to an array substrate, aliquid crystal panel, and a liquid crystal display.

Liquid crystal displays (LCDs) are currently common flat panel displays,and thin film transistor liquid crystal displays (TFT-LCDs) are the mainkind of LCDs. According to the driving method, LCDs can be classifiedinto Twisted Nematic (TN) type, In-Plane Switching (IPS) type, FringeField Switching (FFS) type and so on.

In IPS type and FFS type LCDs, a first electrode and a second electrodefor forming a driving electric field (that is, a pixel electrode and acommon electrode) are both formed on an array substrate. The differencelies in that the first electrode and the second electrode in the arraysubstrate of the IPS type LCD are formed in the same layer, and thefirst electrode and the second electrode in the array substrate of theFFS type LCD are formed in the different layers. In general, a patternof each first electrode has a plurality of slits, or may be called as aslit-shaped pattern having a plurality of elongated slits. In order toprovide the wide view angle LCD, two-domain region design is generallyadopted. In the two-domain region design, the first electrode has tworegions, in one of which the tilt angle of slits is different from thatof slits in the other regions, forming two domains. In each of the tworegions, slits are tilted at a predetermined angle in the plane of thearray substrate and the tilted angle of slits of the two regions aredifferent from each other, and thus, the direction of the electric fieldformed by the first electrode and the second electrode in one of the tworegions is different from that of the electric field formed by the firstelectrode and the second electrode in the other region so as to makeliquid crystal molecules in the two regions to oriented to the differentdirection, and as a result, the optical complementary can be achievedbetween the two regions, and the wide view angle can be obtained.

FIG. 1 shows a top structural schematic view of a conventional FFS typearray substrate, wherein gate lines 2 and data lines 3 are provided on afirst substrate 1, and the data line 3 and the gate lines 2 cross eachother, defining a plurality of pixel units arranged in a matrix form.and each of the pixel units comprises a first electrode 4 having slits,a second electrode 5, and a TFT switch. The second electrodes 5 areformed in the same layer as the gate lines 2, and are connected witheach other via common electrode lines 6, for example, by using bridgelines and via holes. FIG. 1 does not show all of the common electrodelines 6 for connecting the second electrodes 5. The TFT switches arerespectively connected with the gate lines 2, the data lines 3 and thefirst electrodes 4 with the gate electrodes, the source electrodes 8 andthe drain electrodes 9. As shown, a part of the gate line 2 is used asthe gate electrode for each TFT switch. Each of the first electrodes 4corresponds to one pixel unit, and the pattern thereof has slits, andthe slits are obliquely and mirror-symmetrically arranged by taking amidline of the pixel unit as a symmetry axis. For each pixel unit, thegate line 2 and the data line 3 cooperate to supply signal voltage tothe first electrode 4 through the TFT switch, the common electrode line6 supplies a common voltage to the second electrode 5, and the signalvoltage and the common voltage are used to form a driving electric fieldfor driving the liquid crystal molecules to orient to a direction, sothat light can be selectively transmitted through a liquid crystal paneland an image can be displayed.

SUMMARY

An embodiment of the present invention provides an array substrate,comprising: a first substrate; and a plurality of gate lines and aplurality of the data lines provided on the first substrate, wherein theplurality of gate lines and the plurality of the data lines cross eachother to define a plurality of pixel units arranged into a matrix form,and each of the plurality of pixel units comprises: a first electrodecomprising two or more regions which have slits at different tiltdegrees from each other; a second electrode; and a thin film transistor(TFT) switch, wherein in each pixel unit, the first electrode and thesecond electrode form a horizontal electric field for driving inoperation, the gate line for the pixel unit and the thin film transistorswitch are arranged between regions of the first electrode, and the thinfilm transistor switch is controlled by the gate line to operate eachregion of the first electrode.

An embodiment of the present invention provides a liquid crystal panel,comprising an array substrate according to any of embodiments of thepresent invention, a color filter substrate facing the array substrate,and a liquid crystal layer between the array substrate and the colorfilter substrate, wherein the color filter substrate comprises a secondsubstrate and, on the second substrate, color filters and a black matrixwhich are formed.

An embodiment of the present invention provides a liquid crystaldisplay, comprising an external frame, a driving device and the liquidcrystal panel according to any of embodiments of the present invention.

Further scope of applicability of the present invention will becomeapparent from the detailed description given hereinafter. However, itshould be understood that the detailed description and specificexamples, while indicating preferred embodiments of the invention, aregiven by way of illustration only, since various changes andmodifications within the spirit and scope of the invention will becomeapparent to those skilled in the art from the following detaileddescription.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description given hereinafter and the accompanying drawingswhich are given by way of illustration only, and thus are not limitativeof the present invention and wherein:

FIG. 1 is a top structural schematic view of a conventional FFS typearray substrate;

FIG. 2 is a top structural schematic view of a pixel unit in theconventional array substrate;

FIG. 3 is a display effect schematic view of the pixel unit in theconventional array substrate;

FIG. 4A is a top partial structural schematic view of an array substrateaccording to a first embodiment of the present invention;

FIG. 4B is a enlarged structural schematic view of a circle in FIG. 4A

FIG. 5 is a top partial structural schematic view of an array substrateaccording to a second embodiment of the present invention;

FIG. 6A is a top partial structural schematic view of an array substrateaccording to a third embodiment of the present invention;

FIG. 6B is a enlarged structural schematic view of a circle in FIG. 6A;

FIG. 7 is a top partial structural schematic view of an array substrateaccording to a fourth embodiment of the present invention;

FIG. 8 is a top partial structural schematic view of an array substrateaccording to a fifth embodiment of the present invention; and

FIG. 9 is a top partial structural schematic view of a color filtersubstrate according to a sixth embodiment of the present embodiment.

DETAILED DESCRIPTION

Embodiment of the invention being thus described, it will be obviousthat the same may be varied in many ways. Such variations are not to beregarded as a departure from the spirit and scope of the invention, andall such modifications as would be obvious to those skilled in the artare intended to be included within the scope of the following claims.

The inventors have found that when displaying an image, the arraysubstrate as shown in FIG. 1 has the following disadvantages. As shownin FIG. 2, at the midline of each pixel unit, the tilted slitspositioned on both sides thereof intersects, so the irregular slitpattern is formed around the midline of the pixel unit, and as a result,when an image is displayed, an accurate electric field for making liquidcrystal molecules to orient cannot be formed at or around the midline ofthe pixel unit, and the liquid crystal molecules got out of control andthe alignment of the liquid crystal molecules are disordered so that adark spot may be formed in the pixel unit as shown in FIG. 3. Therefore,a LCD configured as shown in FIG. 1 has degraded display quality.

First Embodiment

FIG. 4A is a top partial structural schematic view of an array substrateaccording to a first embodiment of the present invention, and this topview do not show insulation layers for simplicity. The array substratecomprises a first substrate 1 and gate lines 2 and data lines 3 arrangedon the first substrate 1. The data lines 3 and the gate lines 2 crosseach other to define a plurality of pixel units arranged into a matrixform, and each of the plurality of pixel units comprises a firstelectrode 4 having slits, a second electrode 5, and a TFT switch, andthe first electrode 4 and the second electrode 5 are used to form anelectric field for driving liquid crystal molecules. Further, the arraysubstrate may comprise common electrode lines 6 for connecting thesecond electrodes 5 which works as a common electrode. In each of thepixel units, the first electrode 4 having slits comprises a first region41 and a second region 42; the gate line 2 and the TFT switch arearranged between the first region 41 and the second region 42 of thefirst electrode 4; the TFT switch comprises a gate electrode, a sourceelectrode 8 and a drain electrode 9, and here the gate electrode isconnected with the gate line 2 or a part of the gate line 2, the sourceelectrode 8 is connected with the data line 3, the drain electrode 9 isrespectively connected with the first region 41 and the second region42. In the present embodiment, a part of the gate line 2 is used as thegate electrode; however, in another example, a portion protruding fromthe gate line 2 may be used as the gate electrode. The array substratehaving the above mentioned structure may be of IPS type or FFS type; inthe present embodiment, the FFS type is taken as a example forexplaining, the second electrode 5 and the first electrode 4 arearranged in the different layers, and the second electrode 5 is disposedcloser to the first substrate 1 than the first electrode 4 so as to formthe FFS type array substrate. The second electrode 5 may be arranged inthe same layer as the gate line 2 or the data line 3, or the firstelectrode 4 is disposed more closer to the first substrate 1 than thesecond electrode 5 as long as the second electrode 5 and the firstelectrode 4 are formed in the different layers. The second electrode 5may be divided into two regions to respectively correspond to those ofthe first electrode 4; or the second electrode 5 may have one regionsforming below the two regions 41 and 42 of the first electrodes 4.

Among conductive structures of the array substrate, such as the gatelines 2, the data lines 3, the common electrode lines 6, the firstelectrodes 4 having slits, the second electrodes 5 and the TFT switches,two or more are required to connect to each other by being arranged inthe same layer or by using via holes, and with regard to theseconductive structures that need not to be connected with each other maybe insulated from each other by forming gaps in the same layer asthereof or by arranging insulation layers.

The present embodiment provides a typical structure, wherein the firstelectrodes 4 have slits, and each of first electrodes 4 corresponds toone pixel unit. The second electrode 5 has a plate-shaped patterncorresponding to one pixel unit, and a plurality of the second electrode5 are arranged into a matrix on the first substrate 1 and connected witheach other with common electrode lines 6. The second electrode 5 may beformed directly on the first substrate 1 in an individual patterningprocess or together with the gate lines 2. The material of the firstelectrode 4 and the second electrode 5 can be a transparent conductivematerial, such as indium tin oxide (ITO) or indium zinc oxide (IZO). Thecommon electrode lines 6 can be formed in the same layer as the gatelines 2, in which case the common electrode lines 6 can be connectedwith each other by using bridge via holes formed in a gate insulationlayers covering the gate lines 2. Alternatively, the common electrodelines 6 may be formed in the same layer as the data lines 3 andconnected with the second electrodes 5 by via holes, or may be arrangedin the same layer as the second electrodes 5 to connect the secondelectrodes 5 together. The data lines 3 and an active layer, the sourceelectrode 8 and the drain electrode 9 of each TFT switch are formedabove the gate insulation layer and then are covered and protected by apassivation layer. The first electrodes 4 are formed above thepassivation layer and are each connected with the drain electrodes 9 byusing via holes 11 formed in the passivation layer.

In the present embodiment, the gate line 2 and the TFT switch arearranged between each two regions of the first electrode 4 in each pixelunit but not between the adjacent two first electrodes 4 of differentpixel units, thus dividing the first electrode 4 into the first region41 and the second region 42, and the drain electrode 9 of the TFT switchis respectively connected with the first region 41 and the second region42, as shown in FIG. 4B which is a enlarged structural schematic view ofa circle in the FIG. 4A.

The above embodiment is especially adapted to the two-domain regiondesign. In the two-domain region design as shown in FIG. 1, the tworegions of the first electrode are connected with each other and formedinto one integral body; however, in the two-domain region design of thepresent embodiment, the first electrode 4 comprises the first region 41and the second region 42, and the two individual regions 41 and 42 arenot connected with each other directly, and slits of the first region 41and slits of the second region 42 are mirror-symmetrically arranged bytaking the gate line 2 as a symmetry axis, and the angle between theslits of the first region 41 and the gate line 2 and the angle betweenthe slits of the second region 42 and the gate line 2 are both largerthan 0 degree and smaller than 90 degree.

In a two-domain region design where the first electrode of each pixelunit is divided into two regions, with the above mentioned embodiment,the gate line and the TFT switch are used to separate the two regions ineach pixel unit so as to avoid occurring of a dark spot in the pixelunit due to liquid crystal molecules out of control at a boundary of thetwo regions having the different slit directions, and therefore thedisplay quality is improved. The gate lines and the TFT switches of thearray substrate are generally shaded by a black matrix from light, thuswith the gate line and the TFT switch directly separating and connectingthe two regions of the first electrode, not only the inverse influenceon the display effect due to an additional pattern for connecting thetwo regions can be avoided, but also it is unnecessary to form anadditional pattern in manufacturing, and further, the aperture ratio ofthe pixel unit of the array substrate is not influenced.

Second Embodiment

FIG. 5 is a top partial structural schematic view of an array substrateaccording to a second embodiment of the present invention. Thedifference between the present embodiment and the first embodiment liesin that the first electrode 4 of each pixel unit can comprise more thantwo individual regions, and for example, the first electrode 4 maycomprises four individual regions. The four regions are referred to as afirst region 41, a second region 42, a third region 43 and a fourthregion 44, as shown in FIG. 5, and a gate line 2 is respectivelyconnected with each region of the first electrode 4 by a drain electrode9 of a TFT switch. More specifically, the pattern of the drain electrode9 are designed to have four branches for connecting each region of thefirst electrode 4 as shown in FIG. 5; in another example, two or fourTFT switches may be provided to make the drain electrodes 9 thereof toconnect respective regions of the first electrode. The number of the TFTswitch may be determined according to the aperture ratio of the pixelunit, a driving current required by each region of the first electrode 4and so on.

With the array substrate having the above mentioned structure, the gateline and the TFT switch are used to separate and connect the regions ofthe first electrode in each pixel unit, so that all regions of the firstelectrode in each pixel unit are maintained the at same potential level,and an additional pattern is not necessary for connecting each region,and thus, the influence on the display effect can be avoided.

Based on the above analysis, the array substrate according toembodiments of the present invention satisfy the following structuralfeatures: the first electrode having slits comprises two or moreindividual regions; the gate line and the TFT switch are providedbetween regions of the first electrode, or provided between two regionsof the first electrode arranged along one direction. Each TFT switchcomprises the gate electrode, the source electrode and the drainelectrode, the gate electrode is connected with one gate line, thesource electrode is connected with one data line, and the drainelectrode is respectively connected with regions of the first electrode.The number, the size and symmetrical relationship of the regions are notlimited.

The array substrate according to the embodiments of the presentinvention can be applied to an IPS type array substrate, in which thesecond electrode and the first electrode are formed in the same layer,the second electrode has slits and comprises two or more individualregions, slits of each region of the second electrode are provided tointersect slits of the corresponding region of the first electrode. Bytaking the second electrode having two regions as an example, the tworegions can be referred to as a fifth region and a sixth region, slitsof the fifth region are provided to intersect slits of the first region,and slits of the sixth region are provided to intersect slits of thesecond region so that the horizontal electric field may be formed overthe array substrate. The common electrode lines may be formed in thelayer in which the data lines, the gate lines or the first electrodesare formed, and connect the second electrodes directly or via holeconnection structure. Slits of the first electrode and the secondelectrode may be mirror-symmetrically arranged to form a certain angleby taking the gate line as a symmetry axis. With the above mentionedembodiment, each region of the first electrode can be separated andconnected, so the aperture ratio of each pixel unit is not influencedand the display quality can be improved.

Third Embodiment

FIG. 6A is a top partial structural schematic view of an array substrateaccording to a third embodiment of the present invention. The presentembodiment may be configured on the basis of each of the previousembodiments; the edges the first region 41 and the second region 42 ofeach first electrode 4, which are adjacent to the corresponding gateline 2, are oblique, and these oblique edges are respectively parallelto slits of the respective regions. FIG. 6B is an enlarged structuralschematic view of a circle in FIG. 6A.

In order to match the shape of the first electrode 4 of the pixel unit,the shape of the gate line 2 positioned between the first region 41 andthe second region 42 is preferably in a triangle, and the shape of thetriangle matches the oblique edges of the regions, that is, edges of thetriangle are substantially parallel to the oblique edges, and thus, thegap of the first electrode 4 and the gate line 2 is reduced as far aspossible, the aperture ratio of the pixel unit can be improved.

The first region and the second region of the first electrode in thepresent embodiment are of a right-angled trapezium shape. In addition,the shape that satisfies the condition that edges of the first regionand the second region of the first electrode adjacent to thecorresponding gate line are oblique edges and the oblique edges arerespectively parallel to respective slits may be non-right-angledtrapezium shape and the like. One pair of parallel sides of thetrapezium adjacent to data lines are parallel to data lines, one of theother pair of sides adjacent to the gate line is as oblique edgeparallel to the slits of the regions.

With the first electrode having the above mentioned shape, edges of thefirst electrodes of the adjacent pixel units may be parallel to eachother, and in this case, upper sides of the parallel sides of thetrapeziums of the first electrodes in the same column alternately facetoward the data lines one both sides of this column of first electrodes,such as, the upper sides of the parallel sides of the trapeziums of thefirst electrodes in odd rows of the same column face toward the datelines on one side of this column first electrodes, and the upper sidesof the parallel sides of the trapeziums of the first electrodes in evenrows of the same column face toward the data lines on the other side ofthis column first electrodes.

Fourth Embodiment

FIG. 7 is a top partial structural schematic view of an array substrateaccording to a fourth embodiment of the present invention. The presentembodiment may be configured on the basis of the previously describedembodiments; the profiles of the first region 41 and the second region42 of each first electrode 4 are in a parallelogram shape, and one pairof the parallel sides of each region in a parallelogram shape adjacentto the data line are parallel to data lines 3 and the other pair of theparallel sides thereof are respectively parallel to slits of thisregion, and preferably, patterns of the first electrodes 4 in theadjacent pixel units match each other, that is, all quadrangles aremirror-symmetrically arranged, and oblique edges of the first electrodes4 between the perpendicularly adjacent two pixel units are parallel toeach other.

The shape of wires positioned between the adjacent two pixel units maybe correspondingly adjusted, for example, the shape of the commonelectrode line 6 is changed from the straight line to the fold line soas to adapt to the shape of the first electrode 4 and improve theaperture ratio of the pixel unit as far as possible. The shape of thegate line 2 positioned between the first region 41 and the second region41 is preferably a triangle, and the shape of the triangle matches theoblique edges of the first electrode, that is, the bevel edge of thetriangle is parallel to the oblique edge of the first electrode 4.

In order to match the shape of the TFT switch with the correspondinggate line 2 of a triangle shape, that is, the shape of the triangle gateelectrode, the source electrode 8 and the drain electrode 9 of the TFTswitch are respectively in a linear shape and a “U” shape, an opening ofthe U shape electrode is arranged toward a bevel edge of the triangle orto face away from the bevel edge of the triangle. For a TFT switch ofthe first row gate line 2 shown in FIG. 7, the drain electrode 9 is in alinear shape, and the source electrode 8 is in a U shape. Alternatively,for a TFT switch of the second row gate line shown in FIG. 7, the sourceelectrode 8 is in a linear shape, and the drain electrode 9 is in a Ushape. In the present embodiment, the TFT switches of all the pixelunits in one row are connected with the data lines 3 on the same side ofthe pixel units, and there is no necessary to change the driving lineconfiguration.

Fifth Embodiment

FIG. 8 is a top partial structural schematic view of an array substrateaccording to a fifth embodiment of the present invention. The presentembodiment may be configured on the basis of the previously describedembodiments, and the difference between the present embodiment and thefourth embodiment lies in that the TFT switches of all pixel units inthe same column are alternately connected with the data lines 3 on bothsides thereof, and not connected with the data lines on the same side.

That is to say, with regard to one column of pixel units, the first rowpixel unit is driven by the data line on one side thereof, and thesecond row pixel unit is driven by the data line on the other sidethereof, and row by row alternation is established. Such configurationdesign of the pixel units makes the pattern of the electrodes of thepixel unit match the patterns of the gate line and the TFT switch inorder to reduce a gap between the electrodes and conductive lines as faras possible, so that the aperture ratio of the pixel unit can beimproved. In this case, the driving method can be correspondinglyadjusted to match the structure of the pixel units, that is, two columndata lines are used to alternately drive one column of pixel units indisplaying an image.

Sixth Embodiment

FIG. 9 is a top partial structural schematic view of a color filtersubstrate according to a sixth embodiment of the present embodiment. Thesix embodiment provides a liquid crystal panel, and the liquid crystalpanel comprises a color filter substrate and an array substrate of anyof embodiments of the present invention, the two substrates areassembled together facing each other to form the liquid crystal panel,and a liquid crystal layer is filled between the two substrates. Thecolor filter substrate comprises a second substrate and color filters 12and a black matrix 13 provided on the second substrate. The pattern ofthe black matrix 13 corresponds to the patterns of the data lines 3, thegate lines 2 and the TFT switches on the array substrate. Further, partsof the black matrix 13 are arranged to correspond to positions betweenthe adjacent first electrodes 4, as shown in FIG. 9. In FIG. 9, theregions having the same shadow patterns represent the color filters 12of the same color, the regions of two color filter resins 12 of the samecolor constitutes one pixel unit to match the pixel unit havingtwo-domain regions on the array substrate according to the abovementioned embodiments.

The black matrix shields the TFT switches from light to protect the TFTswitches so as to avoid occurring of photo-sensing current caused bylight radiating channels of the TFT switches, and simultaneously,because the TFT switches are positioned each at the boundary betweenregions having the different slit direction in one pixel unit, theregion in which orientation of liquid crystal molecules becomedisordered is blocked by the black matrix. The black matrix blockingregions between the adjacent first electrodes can avoid the occurring ofthe color crosstalk between the adjacent pixel units.

An embodiment of the present invention further provides a liquid crystaldisplay, comprising an external frame, a driving device and a liquidcrystal panel according to any of embodiments of the present invention.The liquid crystal panel is mounted within the external frame, connectedwith the driving device and displays images under the control of thedriving device. The liquid crystal display can be used for a computer ora TV set, for example.

With embodiments of the present invention, when a first electrode havingslits on an array substrate need to be divided into different regionsspaced from each other, a gate line and a TFT switch can directly beused to separate the different regions and connect the differentregions, and thus, an additional connection pattern become unnecessary,and the aperture ratio is not disadvantageously influenced, and further,the influence of the abnormal pattern between regions on the displayquality can be avoided. The improvement of the aperture ratio can inturn increase display area and luminance, and thus, the requiredluminance of a backlight can be reduced, and the energy can be saved.When the aperture ratio is increased by 10%, the power consumption ofthe backlight can be reduced by 15%.

The embodiments of the invention being thus described, it will beobvious that the same may be varied in many ways. Such variations arenot to be regarded as a departure from the spirit and scope of theinvention, and all such modifications as would be obvious to thoseskilled in the art are intended to be included within the scope of thefollowing claims.

1. An array substrate, comprising: a first substrate; and a plurality ofgate lines and a plurality of the data lines provided on the firstsubstrate, wherein the plurality of gate lines and the plurality of thedata lines cross each other to define a plurality of pixel unitsarranged into a matrix form, and each of the plurality of pixel unitscomprises: a first electrode comprising two or more regions which haveslits at different tilt degrees from each other; a second electrode; anda thin film transistor (TFT) switch, wherein in each pixel unit, thefirst electrode and the second electrode form a horizontal electricfield for driving in operation, the gate line for the pixel unit and thethin film transistor switch are arranged between regions of the firstelectrode, and the thin film transistor switch is controlled by the gateline to operate each region of the first electrode.
 2. The arraysubstrate of claim 1, wherein in each pixel unit the gate line and thethin film transistor switch are provided between two regions of thefirst electrode arranged along one direction.
 3. The array substrate ofclaim 1, wherein the first electrode of each pixel unit comprises afirst region and a second region which have slits at different tiltdegrees from each other, the slits of the first region and the slits ofthe second region are mirror-symmetrically arranged by taking the gateline therebetween as a symmetry axis, and an angle between the slits andthe gate line are larger than 0 degree and smaller than 90 degree. 4.The array substrate of claim 1, wherein the first electrode of eachpixel unit comprises a first region, a second region, a third region anda fourth region which have slits at different tilt degrees from eachother, the slits of the first region and the slits of the third regionare mirror-symmetrically arranged by taking the gate line as a symmetryaxis, and the slits of the second region and the slits of the fourthregion are mirror-symmetrically arranged by taking the gate line as asymmetry axis.
 5. The array substrate of claim 1, wherein an edge ofeach region of the first electrode adjacent to one gate line is anoblique edge, and the oblique edge is parallel to the slits of thisregion of the first electrode.
 6. The array substrate of claim 5,wherein a shape of the gate line positioned between two regions of onefirst electrode is a triangle, and two edges of the triangle areparallel to the adjacent oblique edges of the regions of the firstelectrode.
 7. The array substrate of claim 1, wherein edges of the firstelectrodes of adjacent pixel units are parallel to each other.
 8. Thearray substrate of claim 1, wherein a profile of each region of eachfirst electrode is in a parallelogram shape, one pair of parallel sidesof the parallelogram shape adjacent to data lines are parallel to thedata lines, and the other pair of parallel sides thereof arerespectively parallel to the slits of respective region of the firstelectrode, and edges of the first electrodes of adjacent pixel units areparallel to each other.
 9. The array substrate of claim 1, wherein ashape of the gate line positioned between two regions of each firstelectrode is a triangle.
 10. The array substrate of claim 9, wherein asource electrode and a drain electrode of each TFT switch arerespectively in a linear shape and a U shape, and an opening of the Ushape is arranged toward a bevel edge of the triangle.
 11. The arraysubstrate of claim 1, wherein the TFT switches of the pixel units of onecolumn are connected with the data line on the same side of the column.12. The array substrate of claim 1, wherein the TFT switches of all thepixel units in a same column are alternately connected with the datalines on both sides of the column.
 13. The array substrate of claim 1,wherein the second electrode and the first electrode of each pixel unitare provided in the different layers.
 14. The array substrate of claim1, wherein the second electrode and the first electrode of each pixelunit are provided in the same layer, the second electrode comprises twoor more regions respectively corresponding to those of the firstelectrode and having slits at different tilt degrees from each other,and the slits of each region of the second electrode intersect the slitsof the corresponding region of the first electrode.
 15. A liquid crystalpanel, comprising: an array substrate according to claim 1, a colorfilter substrate facing the array substrate; and a liquid crystal layerbetween the array substrate and the color filter substrate; wherein thecolor filter substrate comprises a second substrate and, on the secondsubstrate, color filters and a black matrix which are formed.
 16. Theliquid crystal panel of claim 15, wherein the black matrix is arrangedto correspond to the data lines, the gate lines and the TFT switches onthe array substrate.
 17. The liquid crystal panel of claim 16, whereinthe black matrix further comprises portions corresponding to regionsbetween adjacent pixel units on the array substrate.
 18. A liquidcrystal display, comprising: an external frame, a driving device, andthe liquid crystal panel according to claim 15.